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| Preliminary W928C73 POCSAG MICROCONTROLLER GENERAL DESCRIPTION The W928C73 is a high performance 8 bits microcontroller with build-in POCSAG decoder and LCD driver. It is possible to switch the normal mode, idle mode and power down mode for power saving purpose. The W928C73 is an extended C from standard 8031 (excluding UART) that it can be easily applied to pager system or other telecommunication system. FEATURES * 512, 1200 and 2400 bps POCSAG decoder * 6 independent user addresses * Instruction set compatible with MCS51 * System clock - OSC2: 76.8 KHz * 128 bytes on-chip fast RAM * 384 bytes on-chip MOVX RAM * 16K bytes on-chip program ROM * 32 x 32 bits on-chip flash RAM * Timer - Two 16-bit timer/counters - One RTC timer - One Watch-dog timer * * * * * * * * * * - One Buzzer timer Four 8-bit bit-addressable I/O ports Three external interrupt source, INT0, INT1 (BAT_DET_INT), INT3 (KEY_INT) Battery low detector Battery detector Power fail detector Power down wake-up via external interrupts Two 16-bit Data Pointers (Selected by DPS.0) 10 source, 10 vector interrupts structure with two priority-level interrupts Built-in programmable power-saving modes - Idle mode & Power-down mode Operating voltage range: 2.4V to 3.3V * 32 segment x 4 common, 1/3 bias, 1/4 duty LCD driver output * Packaged in 64-pin LQFP -1- Publication Release Date: June 2000 Revision A1 Preliminary W928C73 PIN CONFIGURATION X I N 2 X O U T 2 V D D P 0.6 / K E Y 2 P 0.5 / K E Y 1 P 0.4 / K E Y 0 C O M 3 C O M 2 C O M 1 C O M 0 P 2.3 P/ 2.4 S E PPPVG 2.7 2.6 2.5 3 35 P 2.2 / S E G 34 Vss RESET P1.5/MOTOR P1.6/BUZZER P1.7/LED BL_RF DI BS1 BS2 BS3 EA TEST1 TEST2 PSEN P3.0 P3.1 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 W928C73 64 LQFP SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 P 3.2 / I N T 0 P 3.3 / I N T 1 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9 S E G 10 S E G 11 S E G 12 S E G 13 -2- Preliminary W928C73 PIN DESCRIPTIONS SYMBOL VSS RST P1.5 P1.6 P1.7 BL_RF DI BS1 BS2 BS3 EA TEST1 TEST2 PSEN TYPE I IH O O O I I O O O I I I O I/O I/O I/O I O O O O O O O O O O O O O O GROUND: ground potential DESCRIPTIONS RESET: A low on this pin for two machine cycles while the oscillator is running resets the device. Motor output, hi-drive Buzzer clock output, hi-drive LED output, hi-drive Connect to LVS of IF chip POCSAG signal input RF control 1 RF control 2 RF control 3 External access enable pin. Should connect to VDD. No connection. Test pin. Internal pull low No connection. Test pin. Internal pull low No connection. Test pin. Bit addressable general I/O port 3.0 Bit addressable general I/O port 3.1 Bit addressable general I/O port 3.2 or INT0 defined by SFR Battery fail interrupt input. Connect to V1.5. If voltage potential of battery is less than the 0.8V, the INT1 interrupt flag will be set. LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out P3.0 P3.1 P3.2/INT0 P3.3/INT1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 -3- Publication Release Date: June 2000 Revision A1 Preliminary W928C73 Pin Descriptions, continued SYMBOL SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 P2.2/SEG34 P2.3/SEG35 P2.4/VDD3 P2.5 P2.6 P2.7 COM0 COM1 COM2 COM3 P0.4 P0.5 P0.6 VDD XOUT2 XIN2 TYPE O O O O O O O O O O O O O O O O O O I I/O I/O I/O O O O O I I I I O I LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD segment signal out LCD voltage input (VDD) I/O pin I/O pin I/O pin DESCRIPTIONS LCD common signal output pins. LCD common signal output pins. LCD common signal output pins. LCD common signal output pins. Bit addressable general I/O port 0.4 and Key_0 interrupt Bit addressable general I/O port 0.5 and Key_1 interrupt Bit addressable general I/O port 0.6 and Key_2 interrupt POWER SUPPLY: Supply voltage for operation. Output pin for clock_2. It is the inversion of XIN2. Input pin for clock_2 Note 1: I/O TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain -4- Preliminary W928C73 BLOCK DIAGRAM P0.3 P0.7 P1.0 P1.2 P1.5 P1.7 P3.0 P3.3 Port 0 ACC B Port 2 P2.5 P2.7 T1 register Port 1 PSW T2 register Port 4~8 Stack ALU Pointer P4.0~4.7 P5.0~5.7 P6.0~6.7 P7.0~7.7 P8.0~8.3 Port 3 128B MOV RAM SFR LCD_OFF DPTR DPTR 1 PC 384B MOVX RAM Address bus LCD_ON I N T E R R U P T Timer 0 Timer 1 Buzzer Timer RTC Timer Watchdog Timer 1K FLASH RAM 16KB program ROM 32x4 LCD Address REG Driver Instruction Decoder & Sequencer RESET Power on & power low reset System control Clock Generator L_Clock XIN2 XOUT2 Data bus -5- Publication Release Date: June 2000 Revision A1 Preliminary W928C73 FUNCTIONAL DESCRIPTION The W928C73 is a high performance 8 bits POCSAG microcontroller with build-in LCD driver and POCSAG decoder. The uC is 8031 instruction set compatible with one addition: DEC DPTR (op-code A5H, the DPTR is decreased by 1). The W928C73 has all the standard features of the 8031 except the UART, and has a few extra peripherals and features like watchdog, RTC, buzzer timers, LCD driver, and build-in POCSAG decoder. The W928C73 features a faster running and better performance 8-bit CPU by reducing the machine cycle duration from the standard 8031 period of twelve clocks to four clock cycles for the majority of instructions. The W928C73 also provides dual Data Pointers (DPTRs) to speed up block data memory transfers. In addition, the W928C73 contains on-chip 384B MOVX SRAM. It only can be accessed by MOVX instruction; this on-chip data memory can be enabled by software commend. Memory Organization The W928C73 separates the memory into two sections, the Program Memory and Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is used for storing data or memory mapped devices. The EA pin must connect to high to access on-chip program ROM. 3FFFH 16 K bytes Program Memory 0200H 0080H System testing 0000H Interrupt vector Program Memory 0000H Internal Data Memory 017FH 384 Bytes Data MOVX RAM FFH EEH 7FH Direct & indirect 00H Addressing RAM Internal Data Memory Special Function Register LCD RAM FFH Direct addressing 80H SFR On-chip memory space of W928C73 Stack The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP), which stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the return address is placed on the stack. There is no restriction as to where the stack can begin in the RAM. By default however, the Stack Pointer contains 07H at reset. The user can then change this to any value desired. The SP will point to the last used value. Therefore, the SP will be incremented and then address saved onto the stack. Conversely, while popping from the stack the contents will be read first, then the SP is decreased. -6- Preliminary W928C73 LCD Data Area When LCD ON, the indirect RAM area EEH-FFH work as the LCD data RAM (LCD00-LCD35). Instruction such as "MOV @R0, #I" (Where R0 = EEH-FFH) are used to control the LCD data RAM. The data in the LCD data RAM (bit7-bit0) are transferred to the segment output pins automatically without program control. When the bit value of the LCD data RAM is "1", the LCD is turned on. When the bit value of the LCD data RAM is "0", LCD is turned off. The relation between the LCD data RAM and segment/common pins is shows below. LCD Data RAM EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FFH COM3 BIT 7 COM2 BIT 6 COM1 BIT 5 COM0 BIT 4 COM3 BIT 3 COM2 BIT 2 COM1 BIT 1 COM0 BIT 0 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG25 SEG27 SEG29 SEG35 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG34 -7- Publication Release Date: June 2000 Revision A1 Preliminary W928C73 Descriptions Of Special Function Registers(SFRS) ADDRESS /NAME 80H/P0 BIT B7 B6 B5 B4 B3 B2 B1 B0 81H/SP 82H/DPL 83H/DPH 84H/DPL1 85H/DPH1 86H/DPS 87H/PCON B7~0 B7~0 B7~0 B7~0 B7~0 B0 B7 B6 B5 B4 B3 B2 B1 B0 Key_2 Key_1 Key_0 DEC_ADDT F_ADR DEC_ SYNVAL F_data SP DPL DPH DPL1 DPH1 DPS.0 SMOD SMOD0 GF1 GF0 PD IDL W W Enable Enable Disable Disable BIT NAME R/W R R R R R W R R/W R/W R/W R/W R/W R/W R/W Pointer 1 Pointer 0 SYNC Lost SYNC Matched Unmatched 1 0 INITIAL 1 1 1 1 1 1 1 1 No use Key_2 input. A corresponding key_INT(INT3_3) can be enabled. Key_1 input. A corresponding key_INT(INT3_3) can be enabled. Key_0 input. A corresponding key_INT(INT3_3) can be enabled. POCSAG address matched flag. A corresponding INT(INT2) could be setup. Flash ROM serial address output Decoder synchronization condition Flash ROM data I/O FUNCTION 00000111 Stack pointer address. Always points to top of the stack. 00000000 Low byte of 16 bit data pointer 00000000 High byte of 16 bit data pointer 00000000 Low byte of 16 bit data pointer 1 00000000 High byte of 16 bit data pointer 1 0 0 0 0 0 0 0 0 0 Selection of data pointer, B7~1 are not used No use. Clear to "o" after power_on reset No use. Clear to "o" after power_on reset No use. Clear to "o" after power_on reset No use. Clear to "o" after power_on reset General purpose user defined flag General purpose user defined flag Power down mode enable bit. Set this bit to "1" will stop the CPU and oscillation. Idle mode enable bit. Set this bit to "1" will stop the CPU clock, but the oscillator keep running. Timer 1 overflow flag,. TF1 will automatically clear after INT service routine. Timer 1 enable Timer 0 overflow flag, TF0 will automatically clear after INT service routine Timer 0 enable Interrupt 1(battery fail INT) flag. Set by hardware when a pre-selected INT level (high or low) is detected on INT1. The INT flag will keep only if the level is held. 88H/TCON B7 TF1 R/W Overflow 0 B6 B5 TR1 TF0 W R/W Enable Overflow Disable 0 0 B4 B3 TR0 IE1 (Bat_fail) R/W R/W Enable INT Disable No INT 0 0 -8- Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS /NAME BIT B2 BIT NAME IT1 R/W R/W 1 High level 0 Low level INITIAL 0 FUNCTION Interrupt 1 level selection. Set by software to specify high (>0.8V) / low (<0.8V) level external INT 1 triggered. Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0. This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the pin. Interrupt 0 type selection. Set/cleared by software to specify falling edge/ low level triggered external inputs Timer 1 & timer 0 control: Tx_GATE (gating control): When this bit is set, Timer/counter x will be enabled if both INTx pin is high and TRx control bit is set. When this bit is cleared, Timerx is enabled whenever TRx control bit is set. Tx_C/T (timer or counter select): When cleared, the timer is incremented by internal clocks. When set, the timer counts high-to-low edges of the Tx pin. M1 M0 Mode 0 0 8-bits with 5-bit pre-scalar. 0 1 16-bits, no pre-scalar. 1 0 8-bits with auto-reload from THx 1 1 (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. (Timer 1) Timer/counter is stopped. B1 IE0 R/W INT No INT 0 B0 IT0 R/W Falling edge Low level 0 89H/TMOD B7 T1_GATE R/W 0 B6 T1_T R/W Timer 0 B5 T1_M1 R/W 0 B4 T1_M0 R/W 0 B3 T0_GATE R/W 0 B2 T0_T R/W Timer 0 B1 T0_M1 R/W 0 B0 T0_M0 R/W 0 8AH/TL0 8BH/TL1 8CH/TH0 8DH/TH1 8EH/CKCON B7~0 B7~0 B7~0 B7~0 B7 B6 TL0 TL1 TH0 TH1 WD1 WD0 R/W R/W R/W R/W R/W R/W 00000000 Low byte of timer 0 00000000 Low byte of timer 1 00000000 High byte of timer 0 00000000 High byte of timer 1 0 0 WD1 WD0 (watchdog timeout period) 0 0 Fs/214+512 clock 0 1 Fs/216+512 clock 1 0 Fs/218+512 clock 1 1 Fs/221+512 clock RTC1 RTC0 (RTC timeout period) 0 0 32 Hz for RTLCD = 74 0 1 8 Hz 1 0 2 Hz 1 1 1 Hz B5 RTC1 R/W 0 B4 RTC0 R/W 0 -9- Publication Release Date: June 2000 Revision A1 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS /NAME BIT B3 B2 B1 BIT NAME ELC R/W R/W R/W R/W Enable Disable 1 0 INITIAL 1 1 1 ELC: enable L_clock. Keep this bit high for whole operation. B0 90H/P1 B7 B6 B5 B4 B3 B2 B1 DEC_RST DEC_ON DEC_ DATA B0 91H/PBCON B7 B6 B5 B4 B3 B2 B1 B0 92H/TONE0 96H/PLC 97H/PLH A0H/P2 B7~0 B7~0 B7~0 B7 B6 B5 B4 B3 DEC_CLK ENBT ENBUZ TONE0 PLC PLH P2.7 P2.6 P2.5 P2.4 P2.3 W W W W W W W W W W R R W/R W/R W/R W/R W/R High Low High Low Enable Enable Disable Disable High Low 1 0 0 0 0 0 0 0 0 00000000 00000000 00000000 1 1 1 1 1 No use if SEG35~32 work as LCD segment. I/O P2.3 value if SEG35~32 work as P2.3~P2.0 function (P2M (A1.1H) = 0) B2 B1 P2.2 P2.1 W/R W/R High High Low Low 1 1 I/O P2.2 value if SEG35~32 work as P2.3~P2.0 function (P2M (A1.1H) = 0) No use if SEG35~32 work as LCD segment. I/O P2.1 value if SEG35~32 work as P2.3~P2.0 function (P2M (A1.1H) = 0) Buzzer timer enable (used as a general timer) Buzzer output enable Auto reload value of buzzer timer Low byte of program counter High byte of program counter I/O P2.7 B6~B4 no use when LCD is on. Decoder option setup clock output control bit Clear B7~B2 to 0 after power on reset. EHC LED Buz_out Motor R/W W W W W W W W High High High Low Low Low High High High Low Low Low 0 1 1 1 1 1 1 1 Clear to "0" after reset. LED output port P1.7 (HI-drive) Initial value of buzzer output pin Motor output pin(Hi-drive) No use Decoder reset control bit Decoder enable control bit Decoder option setup data output control bit FUNCTION Set B3 and B2 to 1 after power on reset. - 10 - Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS /NAME BIT B0 BIT NAME P2.0 R/W W/R 1 High 0 Low INITIAL 1 FUNCTION No use if SEG35~32 work as LCD segment. I/O P2.0 value if SEG35~32 work as P2.3~P2.0 function (P2M (A1.1H) = 0) A1H/LCDR B7 B6 B5 B4 B3 LCDWAVE FLCD1 W W W W W A Type B Type 0 0 0 0 0 FLCD1 FLCD0 LCD frequency 0 B2 FLCD0 W 0 0 1 1 0 1 0 1 512 Hz, set RTLCD = 74 256 Hz 128 Hz 64 Hz Clear B7~B4 to "0" after reset. Default LCDWAVE =0 (B type) LCD scan rate = LCD frequency/ 4 B1 P2M W SEG out P2 0 P2.0~2.3/SEG32~35 pin function selection. This bit can only be set while LCD is on. While set to 1, these 4 pins work as SEG32~35 output. If clear to 0, these 4 pins will work as P2.0~2.3. B0 A2H/RTLCD A8H/IE B7~0 B7 B6 B5 B4 B3 B2 B1 B0 AAH/SDTMF B7 B6 B5 B4 B3 B2 B1 B0 LCDON RTLCD EA ES1 ET1 EX1 ET0 EX0 INT33 INT32 INT31 INT30 W W W W W W W W W W W W W W W W W W Enable Enable Enable Enable Enable Enable Enable Enable Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Disable Disable LCD ON LCD OFF 0 LCD driver enable control 11111111 RTC timer value. Set RTLCD = 74 for 76.8 KHz crystal 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Global interrupt enable control POCSAG receiving buffer interrupt enable control Clear this bit to 0 after power on reset Clear this bit to 0 after power on reset Timer 1 interrupt enable control External interrupt 1 (battery fail INT) enable control Timer 0 interrupt enable control External interrupt 0 enable control Clear this bit to 0 after reset Enable INT32 (key2) Enable INT31 (key1) Enable INT30 (key0) Clear B3~B0 after reset - 11 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS /NAME B0H/P3 BIT B7 BIT NAME DEC_BL R/W R 1 Battery low 0 Battery OK INITIAL 1 Battery condition. If battery voltage is lower than 1 volt, this bit will change to 1, otherwise this bit will be 0. This bit works only if BL_RF pin is connect to IF IC LVS output. 1 1 1 1 Flash ROM mode control bit Flash ROM clock output bit Flash ROM control bit Battery fail condition. If battery voltage is lower than 0.8 volt, this bit will change to 0, otherwise this bit will be 1. An additional level interrupt(INT1) can be enabled to monitor this bit. B2 B1 B0 B2/HB B8H/IP B7~0 B7 B6 B5 B4 B3 B2 B1 B0 C0H/CSCON B7 B6 B5 B4 B3 B2 B1 B0 C1H/SMODE C2H/SB1 C3H/SB2 B7~0 B7~0 B7~0 P3.2/INT0 P3.1 P3.0 HB BTF PS1 PT1 PX1 PT0 PX0 OVFH OVFL SIF REN1 SMODE SB1 SB2 R/W R/W R/W R/W W W W W W W W W W W W W R R R W W R R Enable Disable High High High High Low Low Low Low High High Low Low 1 1 1 00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000000 00000000 00000000 No use OSC2 clock stable flag POCSAG receiving buffer interrupt request flag POCSAG receiving buffer enable control POCSAG mode control, Set SMODE = 11101101 after reset POCSAG receiving buffer 1 POCSAG receiving buffer 2 I/O P3.2 & external interrupt 0 input I/O P3.1 I/O P3.0 High byte address of "MOVX @Ri" Buzzer timer interrupt priority level POCSAG receiving buffer interrupt priority level Clear this bit to 0 after reset Clear this bit to 0 after reset Timer 1 interrupt priority level Interrupt 1 (INT1) interrupt priority level Timer 0 interrupt priority level Interrupt 0 (INT0) interrupt priority level Clear B7~B4 to 0 after reset FUNCTION B6 B5 B4 B3 F_Mode F_CLK F_ctrl Bat_fail/ INT1 W W W R High High High Low Low Low Battery Battery OK fail or no battery - 12 - Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS /NAME C4H/SB3 C9H/T2MOD BIT B7~0 B7 B6 B5 B4 B3 B2 B1 B0 D0H/PSW B7 BIT NAME SB3 DME0 TONESEL CY R/W R W W W W W W W W R PWM 50-50duty On-chip External 1 0 INITIAL FUNCTION 00000000 POCSAG receiving buffer 3 1 0 0 0 0 0 0 0 0 MOVX RAM selection (384 bytes), set to 1 after reset Clear this bit to "0" after reset Clear this bit to "0" after reset Clear this bit to "0" after reset Clear this bit to "0" after reset Buzzer tone duty control Clear this bit to "0" after reset Clear this bit to "0" after reset Carry flag: Set for an arithmetic operation which results in a carry being generated from the ALU. It is also used as the accumulator for the bit operations. B6 AC R 0 Auxiliary carry: Set when the previous operation resulted in a carry (during addition) or a borrowing (during subtraction) from the high order nibble. User define flag RS1 RS0 Register bank selection 0 0 1 0 1 Bank 0 Bank 1 Bank 2 Bank 3 00-07(B0-B7) 08-0F(B0-B7) 10-17(B0-B7) 18-1F(B0-B7) 0 1 1 B5 B4 F0 RS1 R/W R/W 0 0 B3 RS0 R/W 0 B2 OV R 0 Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as a result of the previous operation or viceversa. B1 B0 F1 P R/W R 0 0 User defined flag Parity flag: Set/cleared by hardware to indicate odd/even number of 1's in the accumulator. D8H/WDCON B7 B6 RTIF POR R R/W 0 X RTC interrupt request flag Power-on reset flag: Hardware will set this flag on a power up condition. This flag can be read or written by software. A write by software is the only way to clear this bit once it is set. B5 B4 - R/W R/W 0 0 Clear this be after reset Clear this be after reset - 13 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS /NAME D8H/WDCON BIT B3 BIT NAME WDIF R/W R 1 0 INITIAL 0 FUNCTION Watchdog Timer Interrupt Flag: If the watchdog interrupt is enabled, hardware will set this bit to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit indicates that the time-out period has elapsed. B2 WTRF X Watchdog Timer Reset Flag: Hardware will set this bit when the watchdog timer causes a reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit. This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer will have no affect on this bit. B1 B0 EWT RWT X 0 Enable Watchdog timer Reset: Setting this bit will enable the Watchdog timer Reset function. Reset Watchdog Timer: This bit helps in putting the watchdog timer into a know state. It also helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog timer reset will be generated if EWT is set. This bit is selfclearing. R/W control for P0.7 (key3): No use, clear this bit to 0 after. B6 P0IO.6 W 0 R/W control for P0.6 (key2): 1: input mode without pull high R 0: output mode or input with pull high R Clear this bit after reset for key2 input with pull high R function. B5 P0IO.5 W 0 R/W control for P0.5 (key1): 1: input mode without pull high R 0: output mode or input with pull high R Clear this bit after reset for key1 input with pull high R function. B4 P0IO.4 W 0 R/W control for P0.4 (key0): 1: input mode without pull high R 0: output mode or input with pull high R Clear this bit after reset for key0 input with pull high R function. B3 B2 B1 B0 P0IO.3 P0IO.2 P0IO.1 P0IO.0 W W W W 0 0 0 0 R/W control for P0.3: Set this bit to "1" after reset for DEC_ADDT input R/W control for P0.2: Clear this bit to "0" after reset for F_ADR output function R/W control for P0.1: Set this bit to "1" after reset for DEC_SYNVAL input R/W control for P0.0: Set this bit to "1" after reset. For read-in F_data, set this bit to "1". For write-out F_data, clear this bit to "0". D9H/P0IO B7 P0IO.7 W 0 - 14 - Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS /NAME DAH/P1IO BIT B7~0 BIT NAME P1IO R/W W 1 0 INITIAL FUNCTION 00000000 Bit addressable R/W control for P1: 1: input mode without pull high R 0: output mode or input with pull high R Set DA to "00000000 " after reset, since P1 are all output mode. 00000000 Bit addressable R/W control for P2 1: input mode without pull high R 0: output mode or input with pull high R Set DB to "X0000000 " after reset. The value of P2IO.7 depends on the function of P2.7 (input of output) 00000000 Bit addressable R/W control for P3 1: input mode without pull high R 0: output mode or input with pull high R Set DC to "10001XXX " after reset. The values of P3IO.2~P3IO.0 depend on the functions of P3.2~P3.0 (input of output) 0 0 0 0 0 00000000 Accumulator Enable Enable Enable Enable Enable Enable H_clock High High High Falling High Falling High Disable Disable Disable Disable Disable Disable L_clock Low Low Low Rising Low Rising Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC timer and LCD clock enable Buzzer timer interrupt enable RTC timer interrupt enable Watchdog timer interrupt enable External interrupt 3 request flag External interrupt 3 enable External interrupt 2 request flag External interrupt 2 enable System clock selection Buzzer timer interrupt priority RTC timer interrupt priority Watchdog timer interrupt priority INT3 (key_INT) trigger edge selection External interrupt 3 priority INT2 (ADDT) trigger edge selection External interrupt 2 priority Clear DDH to "00" after reset. DBH/P2IO B7~0 P2IO W DCH/P3IO B7~0 P3IO W DDH/P48IO B4 B3 B2 B1 B0 P8IO P7IO P6IO P5IO P4IO ACC ERTLC EBTI ERTI EWDI IE3 EX3 IE2 EX2 B SMSC PBTI PRTI PWDI IT3 PX3 IT2 PX2 W W W W W R/W W W W W R W R W R/W W W W W W W W W E0H/ACC E8H/EIE B7~0 B7 B6 B5 B4 B3 B2 B1 B0 F0/B F8H/EIP B7~0 B7 B6 B5 B4 B3 B2 B1 B0 00000000 B register Notes: 1. The SFRs in bold are bit addressable, others are byte addressable. 2. The SFRs can only be accessed by direct addressing. 3. P2.4 is pulled high internal, when external use VDD to connect p2.4 for LCD. The S/W must do the following instruction mov P2IO,#10H and clr P2.4 4. P0IO~P8IO default are output mode(0), when need input mode then set P0IO~P8IO are 1. - 15 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 Data Pointers The original 8031 had only one 16-bit Data Pointer (DPL, DPH). In the W928C73, there is an additional 16-bit Data Pointer (DPL1, DPH1). This new Data Pointer uses two SFR locations which were unused in the original 8031. In addition there is an additional instruction, DEC DPTR (op-code A5H), which helps in improving programming flexibility for the user. MOVX Instruction The W928C73, like the standard 8031, uses the MOVX instruction to access the external Data Memory. The external data memory includes 384 bytes on-chip data RAM. The MOVX instruction is of two types, the MOVX @Ri and MOVX @DPTR. In the MOVX @Ri, the address of the external data comes from two sources. The lower 8-bits of the address are stored in the Ri register of the selected working register bank. The upper 8-bits of the address are store in the HB register (B2h of SFR). In the MOVX @DPTR type, the full 16-bit address is supplied by the Data Pointer. Since the W928C73 has two Data Pointers, DPTR and DPTR1, the user has to select between the two by setting or clearing the DPS bit. The Data Pointer Select bit (DPS) is the LSB of the DPS SFR, which exists at location 86h. Rest bits in this SFR have no effect, and are set to 0. When DPS is 0, then DPTR is selected, and when set to 1, DPTR1 is selected. The user can switch between DPTR and DPTR1 by toggling the DPS bit. The quickest way to do this is by the INC instruction. The HB register and dual Data Pointers will provide enough flexibility for performing block move operations. SYSTEM CLOCK The W928C73 provides one oscillation circuit, OSC2 - L_clock (76.8 KHz), for the whole system. During the power on reset, the L_clock is activated. The RTC Timer, WDT timer, buzzer output and LCD frequency clock sources directly come from L_clock. The CPU, timer0, timer1 and interrupt operation are based on the machine cycle. The machine cycle consists of four oscillator clock sequence (4 states). ELC is the control bit to activate the L_clock. The OVFL is the clock stable flag for the L_clock. The power on state of system is ELC = 1. For proper operation, the L_clock is suggested to turn on all the time. The clock architecture of the system is shown below. /4 Timer/Counter 0, 1 Interrupt CPU /IDL OSC2 L_Clock WDT,RTC, LCD, BUZ /PD ELC - 16 - Preliminary W928C73 Power Management Operation Mode (Normal Mode) After the power on reset, the W928C73 will enter the normal operation mode. In this mode, all the system is operable with the main clock. Idle Mode While setting the PCON.0 to 1, the system will go to idle mode. In idle mode, the CPU is stopped but rest of the system and the oscillator is still running as previous state The idle mode can be waked up by all the interrupt sources. Power Down Mode The instruction setting PCON.1 is the last executed prior to going into the Power-down mode. In Power-down mode the oscillator is stopped. The contents of the on-chip RAM and SFRS are preserved. The port pins output the values held by their respective SFRs. PSEN are held LOW. In Power-down mode VDD may be reduced to minimize power consumption. However, the supply voltage must not be reduce until Power-down mode is active, and must be restored before the hardware reset is applied and frees the oscillator. Reset must be held active until the oscillator has restarted and stabilized. The wake-up operation of W928C73 after power-down mode has two approaches, wake-up using external interrupt INT0, INT1or wake-up using RESET. For INT0 or INT1 wake-up, the controller will enter the interrupt service routine and is in the slow operation mode and the contents of the on-chip RAM and SFRS are preserved. For RESET wake-up, the RESET pin has to be kept HIGH for a minimum of 24 oscillator periods, the uC will enter the power on reset state after wake up. OPERATION MODE Setting Command NORMAL MODE Power on reset Idle mode wake up 3. Power down mode wake up Oscillator CPU Interrupt Watchdog Timer Timer0, Timer1 RTC Buzzer Timer Release Condition L_clock on Operable All interrupt operable Operable L_clock/4 operable L_clock operable L_clock operable All enabled interrupts Clock keeps oscillation Stopped Clock stops Stopped INT0, INT1 Stopped Stopped Stopped Stopped 1. RESET 2. External interrupt INT0, INT1 Release Time 2 main clock 14 IDLE Set PCON.0 to 1 POWER DOWN Set PCON.1 to1 - 17 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 Timer 0 & 1 The W928C73 has two 16-bit Timer. Each of these Timer has two 8 bit registers which form the 16 bit counting register. For Timer 0 they are TH0, the upper 8 bits register, and TL0, the lower 8 bit register. Similarly Timer 1 has two 8 bit registers, TH1 and TL1. The two can be configured to operate as timers, counting machine cycles. The timer clock is 1/4 of the system clock. The T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the count register is incremented. Since it takes two machine cycles to recognize a negative transition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock frequency. In the "Timer" mode, the recognized negative transition on pin T0 and T1 can cause the count register value to be updated only in the machine cycle following the one in which the negative edge was detected. The "Timer" function is selected by the "C/T" bit in the TMOD Special Function Register. Each Timer has one selection bit for its own; bit 2 of TMOD selects the function for Timer 0 and bit 6 of TMOD selects the function for Timer 1. In addition each Timer can be set to operate in any one of four possible modes. The mode selection is done by bits M0 and M1 in the TMOD SFR. Mode 0 In Mode 0, the timer act as a 8 bit counter with a 5 bit, divide by 32 pre-scale. In this mode we have a 13 bit timer. The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx. The upper 3 bits of TLx are ignored. The negative edge of the clock increments the count in the TLx register. When the fifth bit in TLx moves from 1 to 0, then the count in the THx register is incremented. When the count in THx moves from FFh to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if TRx is set and either GATE = 0 or INT x = 1. When C/ T is set to 0, then it will count clock cycles, and if C/ T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1. When the 13 bit count reaches 1FFFh the next count will cause it to roll-over to 0000h. The timer overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that when used as a timer, the time-base is clock cycles/4. C/T = TMOD.2 (C/T = TMOD.6) System Clock 1/4 M1, M0 = TMOD1, TMOD0 (M1, M0 = TMOD5, TMOD4) 00 TL0 (TL1) 01 TH0 (TH1) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 INT1 = P3.3 Interrrpt TF0 (TF1) Timer 1 functions are shown in brakets Mode 0 and 1 of Timer 0 & 1 - 18 - Preliminary W928C73 Mode 1 Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13 bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in Mode 0. The gate function operates similarly to that in Mode 0. Mode 2 In Mode 2, the timer is in the Auto Reload Mode. In this mode, TLx acts as a 8 bit count register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx bit in TCON is set and TLx is reloaded with the contents of THx, and the counting process continues from here. The reload operation leaves the contents of the THx register unchanged. Counting is enabled by the TRx bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1, mode 2 allows counting of either clock cycles (clock/4) or pulses on pin Tn. C/T = TMOD.2 (C/T=TMOD.6) System Clock 1/4 Timer 1 functions are shown in brakets TL0 (TL1) Interrrpt TF0 (TF1) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 INT1 = P3.3 TH0 (TH1) Mode 2 of Timer 0 & 1 Mode 3 Mode 3 has different operating methods for the two timer. For timer 1, mode 3 simply freezes the counter. Timer 0, however, configures TL0 and TH0 as two separate 8 bit count registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer 0 control bits C/T, GATE, TR0, INT0 and TF0. The TL0 can be used to count clock cycles (clock/12 or clock/4) or 1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle counter (clock/12 or clock/4) and takes over the use of TR1 and TF1 from Timer 1. Mode 3 is used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still be used in Modes 0, 1 and 2., but its flexibility is somewhat limited. While its basic functionality is maintained, it no longer has control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a timer and retains the use of GATE and INT1 pin. In this condition it can be turned on and off by switching it out of and into its own Mode 3. - 19 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 C/T = TMOD.2 System Clock 1/4 TL0 Interrrpt TF0 TR0 = TCON.4 GATE = TMOD.3 INT0 = P3.2 TH0 TR1 = TCON.6 TF1 Interrrpt Mode 3 of Timer 0 & 1 Watchdog Timer The watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. When the time out occurs a request flag is set, which can cause an interrupt or a system reset depend on the EWDI or EWT enable SFR. The interrupt and reset functions are independent of each other and may be used separately or together depending on the users software. The watchdog timer should first be restarted by using RWT. This ensures that the timer starts from a known state. Fosc=76.8KHz L_Clock Divider1 Fosc/8192 9.375Hz WDIF Interrupt EWDI WD1 WD0 4.64 Hz 2.34 Hz 1.17 0.59 0.29 Hz Hz HZ 0.15 0.07 Hz Hz 0.04 Hz divider2 512 clock delay Reset EWT EWDI:E8.4H WD1, WD0:8E.7H, 8E.6H RWT WDIF:D8.3H WTRF:D8.2H EWT:D8.1H RWT:D8.0H WD1~0 Selector WTRF Buzzer Timer The W928C73 provides a buzzer timer. The buzzer timer can output a single tone signal to the BUZ pin that frequency range from 150Hz to 38400 Hz. The operation of buzzer timer is as following. First set the proper value of tone0 then set the ENBUZ to 1, the uC will output the corresponding frequency (50% duty cycle) to P1.6/BUZ output pin. The timer can also generate different duty cycle to control the buzzer volume. - 20 - Preliminary W928C73 The auto-reload condition: 1. When 8 bits down counter overflow (From "01H" change to "FFH") 2. ENBUZ or ENBT signal rising edge (From "L" change to "H") The divider reset condition: 1. RESET 2. MOV TONE,#I instruction 3. ENBUZ rising edge RTC Timer and LCD Frequency The W928C73 provides flexible RTC timer for real time clock calculation. The 8 bit auto-reload downcounter, RTLCD, can download a suitable value for different main clock frequency to generate the clock interrupt. For 76800Hz crystal, the RTLCD value should be 74. This RTC timer is also used to provide the LCD frequency source. LCD Controller/Driver The W928C73 can directly drive a LCD with 32 segment output pins and 4 common output pins for a total of 36 x 4 dots. LCDR is used for the LCD driver control. The alternating frequency of the LCD can be set as 64 Hz, 128 Hz, 256 Hz, or 512 Hz. In addition, LCDON (LCDR.0) bit can also be used to set up four of the LCD driver output pins (segment 0 to segment 31/35) as a I/O port. (For 76.8 KHz and RTLCD = 74). The LCD driving potentials are connected to external through port 2.4~2.6 while LCDON is set to 1. The pin connections and output waveforms for the 1/3 bias, 1/4 duty LCD driving modes are shown below. LCD_ON 1 P2.6 0 Vcc Vlcd3 LCD driver outputs for seg. on COM1 COM2 sides being lit LCD driver outputs for seg. on COM0 COM2,3 sides being lit LCD driver outputs for seg. on COM0 COM1,2,3 sides being lit VDD3 VDD2 VDD1 VSS 1 P2.5 0 Vlcd2 1 P2.4 0 Vlcd1 VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS LCD Voltage Pin Connection and Output Waveform (1/3 Bias 1/4 Duty) - 21 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 I/O Ports The W928C73 has four 8-bit bit addressable I/O ports, port 0 - port 3. The segment and common signal out of LCD driver can change to I/O port if LCD driver is disabled. The additional I/O port 4 - port 8 are byte addressable. Port 4, 5 can be used as an address bus and port 6 can be used as data bus when external program is running or external memory/device is accessed by MOVC or MOVX instruction. The I/O ports of W928C73 are same as 8031 but with extra pull high resister control. While read out the SFR value of port, the port will function as input mode. While write the data to port SFR, the I/O port will work as output port. SFR P0IO-P3IO define the pull high condition of port 0 - port 3. When setting the SFR bit to 1 will set the I/O port as input mode without pull high resister or opendrain output mode. When clear to 0 will set the I/O port as input mode with pull high resister or output mode. Port 0 - port 3 are bit addressable. The initial state of W928C73 is input mode with pull high resister. If LCD is off, P48IO is used to control the pull high resister of port 4 - port 8, and is byte controllable. Interrupt The W928C73 provides 10 interrupt sources with two priority levels. The External interrupt 0 has the highest natural priority. Software can assign high or low priority to each interrupt source. All interrupt source priorities are reset to low. Name INT0 TF0 INT1 TF1 SCON1 INT2 INT3 WDTI RTCI BTI DESCRIPTION External interrupt 0 Timer 0 overflow interrupt External interrupt 1 (BAT_DET_INT) Timer 1 overflow interrupt POCSAG data buffer interrupt External interrupt 2 External interrupt 3 (Key_interrupt) Watchdog interrupt Real-time timer interrupt Buzzer timer interrupt VECTOR 03H 0BH 13H 1BH 3BH 43H 4BH 53H 5BH 63H NATURAL PRIORITY 1 2 3 4 5 6 7 8 9 10 POCSAG Decoder The build-in decoder is fully compatible with CCIR Radio Paging Code Number 1 (POCSAG code) operating at 512, 1200, or 2400 bps. The build-in POCSAG decoder supports 6 user addresses in 6 independent frames. - 22 - Preliminary W928C73 Initial Option Bit Setup The decoder should be initialized through SFR DEC_TXCLK (P1.0), DEC_TXDATA (P1.1), and DEC_RST (P1.3) as Fig 12. Clearing the SFR DEC_ON (P1.2) from high to low after the 192 option bits setting will enable the decoder. The BS1, BS2 and BS3 pins will then control the RF to receive POCSAG signal. The functions of the option bits are described below. DEC_RST (P1.3) Total 192 clock DEC_TXCLK (P1.0) At least 2 mS At least 2 mS ~ ~ At least 1 s DEC_TXDATA (P1.1) D0 D1 D2 D3 D4 D5 ~ ~ D192 DEC_ON (P1.2) BS1 BS2 BS3 - 23 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 POCDSG Decoder Setup Option CLOCK DATA CLOCK DATA CLOCK DATA CLOCK DATA CLOCK DATA CLOCK DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 0 TEST0 TEST1 ADA17 ADA16 ADA15 ADA14 ADA13 ADA12 ADA11 ADA10 ADA9 ADA8 ADA7 ADA6 ADA5 ADA4 ADA3 ADA2 ADA1 ADA0 FA3 FA2 FA1 Baud1 Baud0 Inv Over1 Over0 Smith 0 0 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 0 0 0 ADB17 ADB16 ADB15 ADB14 ADB13 ADB12 ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 FB3 FB2 FB1 EnA EnB EnC EnD EnE EnF 0 0 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 0 0 0 ADC17 ADC16 ADC15 ADC14 ADC13 ADC12 ADC11 ADC10 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 FC3 FC2 FC1 PL1 PL2 PL3 PL4 FIL 0 0 0 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 0 0 0 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 FD3 FD2 FD1 Outr1 Outr2 PREL1 PREL0 0 0 0 0 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 0 0 0 ADE17 ADE16 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 FE3 FE2 FE1 0 0 0 0 0 0 0 0 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 0 0 0 ADF17 ADF16 ADF15 ADF14 ADF13 ADF12 ADF11 ADF10 ADF9 ADF8 ADF7 ADF6 ADF5 ADF4 ADF3 ADF2 ADF1 ADF0 FF3 FF2 FF1 0 0 0 0 0 0 0 0 - 24 - Preliminary W928C73 FUNCTION Address A, B, C, D, E, F Disable Enable OPTION EnA, EnB, EnC, EnD, EnE, EnF 0 1 FUNCTION Message reception error termination condition Reception termination on first uncorrectable codeword Reception termination on two consecutive uncorrectable codeword Reserved Reserved Over1 0 0 1 1 OPTION Over0 0 1 0 1 FUNCTION NRZ Signal Input Without Schmitt Trigger With Schmitt Trigger OPTION Shmt 0 1 FUNCTION Out of range hold time when synchronization lost 512 bps 36 sec 72 sec 144 sec 288 sec 1200/2400 bps 31 sec 61 sec 123 sec 246 sec 0 0 1 1 OUTR1 OPTION OUTR2 0 1 0 1 FUNCTION Baud rate 512 bps 1200 bps 2400 bps Baud0 0 1 1 OPTION Baud1 1 1 0 - 25 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 BS1 32 bits BS3 TBS3 TBS2 BS2 TBS2 FUNCTION TBS2 512 bps 3.90 mS 11.71 mS 19.53 mS 27.34 mS FUNCTION TBS3 512 bps 0.00 mS 31.25 mS 62.50 mS 93.75 mS 1200/2400 bps 0.00 mS 13.33 mS 26.67 mS 40.00 mS 0 0 1 1 PL4 1200/2400 bps 1.67 mS 5.00 mS 8.33 mS 11.67 mS 0 0 1 1 PL2 OPTION PL1 0 1 0 1 OPTION PL3 0 1 0 1 FUNCTION Preamble length 512 bit 896 bit 1024 bit 1792 bit PREL1 0 0 1 1 OPTION PREL0 0 1 0 1 - 26 - Preliminary W928C73 FUNCTION NRZ signal Non-inversion Inversion OPTION Inv 0 1 The option bit TEST0, TEST1 and FIL are only used for IC testing. For normal operation, insert "0" for all those three option bits. POCSAG data output format While receiving an address matched message the SCON1 will generate interrupt and the data will present in SBUF1-3. The value of SBUF for the first interrupt is address word, followed by message words, and ended with the termination word. If another addressed matched message is received right after the first message, the second address word will come out followed by the previous termination word as shown below. The detail formats of address word, message word and termination word are as following: POCSAG Signal Address A Data A1 Data AN Address B DEC_ADDT(P0.3) SINT SBUF3~1 TRM Word of previous message ADR A MSG A1 MSG AN TRM ADR B Address Word Format SB3 BIT 7 FUN21 SB2 BIT 7 A13 BIT 6 A12 BIT 5 A11 BIT 4 A10 BIT 3 A9 BIT 2 A8 BIT 1 A7 BIT 0 A6 BIT 6 FUN20 BIT 5 A19 BIT 4 A18 BIT 3 A17 BIT 2 A16 BIT 1 A15 BIT 0 A14 - 27 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 SB1 BIT 7 A5 BIT 6 A4 BIT 5 A3 BIT 4 A2 BIT 3 ADR2 BIT 2 ADR1 BIT 1 ADR0 BIT 0 CM (0) Note: CM = 0: Address word, CM = 1: Message word, Termination word Func21, 20: function bit of POCSAG ADR2~0: define the received address number ADR2-0 Address 000 A 001 B 010 C 011 D 100 E 101 F Message Word Format SB3 BIT 7 M21 SB2 BIT 7 M13 SB1 BIT 7 M5 BIT 6 M4 BIT 5 M3 BIT 4 M2 BIT 3 SYNC BIT 2 ER0 BIT 1 TM (0) BIT 0 CM (1) BIT 6 M12 BIT 5 M11 BIT 4 M10 BIT 3 M9 BIT 2 M8 BIT 1 M7 BIT 0 M6 BIT 6 M20 BIT 5 M19 BIT 4 M18 BIT 3 M17 BIT 2 M16 BIT 1 M15 BIT 0 M14 Note: SYNC: sync detection / 1: syncloss 0: catch sync ER0: error condition after correction / 1:error 0:No error Termination Word Format SB3 BIT 7 0 SB2 BIT 7 0 SB1 BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 TMC BIT 1 TM (1) BIT 0 CM (1) BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0 Note: TMC (termination condition): 0: proper termination, 1:Termination due to error condition - 28 - Preliminary W928C73 Decoder related SFR SFR NAME P0.1 P0.3 P1.0 P1.1 P1.2 P1.3 P3.7 NAME DEC_SYNVAL DEC_ADDT DEC_TXCLK DEC_TXDATA DEC_ON DEC_RST DEC_BLDET I/O I I/INT O O O O I DESCRIPTION Decoder synchronization Decoder Decoder option bit setup clock Decoder option bit setup data Decoder on/off control Decoder reset control Battery low detector (1V) 32 x 32 bits Flash ROM Operation The W928C73 provides 32 frame x 32 bit flash ROM cell typically used to store the POCSAG addresses and parameters. The single voltage supply eliminates the need for an extra pump circuit during programming and erasing. There are 3 different operation mode, read, program and erase. The different mode is determined by the number of the clocks of the CTRL bit while the SFR MODE is set to high. The programming timing is shown below. Read Mode MODE CTRL ADR CLK DATA 24 clk Tc A24 A23 A1 b1 b2 b3 b4 bn Program Mode MODE min 400uS CTRL ADR CLK 24 clk Tc A1 Tpr Tc Tc b1 b2 b32 Tc b33 b34 Tc b64 DATA A24 A23 32 bits 32 bits Erase Mode MODE CTRL ADR CLK DATA Twe min 50 mS Low Low High-Z - 29 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 Read mode This mode will read out the data from the flash ROM. The first 24 bits of DATA are the starting frame address of reading-out. If DATA is low for these 24 bits, then the output data will start from address "0". The stored data will shift out bit by bit with each clock in. The LSB of data is shifted out first. Program mode This mode will write data into the flash ROM. This flash ROM is programmed on a frame basis. Each frame contains 32 bits of data. The LSB of data is shift in first. The programming time (Tpr) must be more than 400 S. Each programming pulse will increase the frame address by 1. Erase Mode This mode will erase all the data in the flash ROM. The typical whole-chip-erase time should be larger than 50 mS (Twe). TIMING WAVEFORMS Flash ROM Programming Read Cycle 1/F CLK Write Cycle 1/F CLK CLK DATA T RA CLK DATA TWS TWH T RH Address Shift-in Cycle 1/F ADDR Mode Select Duration ADDR DATA TAS TAH MODE CTRL TMB 1/FCTRL TME - 30 - Preliminary W928C73 Flash Programming SFR Configuration SFR NAME P0.0 P0.2 P3.4 P3.5 P3.6 * * * * * NAME DATA ADDR CTRL CLK MODE I/O I/O O O O O DESCRIPTION Bi-direction data line Output clock for start address shift-out Enable signal for program and erase operations when MODE = 0 (P3.6) Input clock for mode counter when MODE = 1 (P3.6) Output clock for data write-out and read-in Mode select control pin Fast frame-write operation: Frame (32 bits) program cycle time: 400 S (typical) Fast whole-chip-erase duration: 50 mS (max.) Read data access time: 500 nS (max.) Program/erase cycles: 3000 (typical) Data retention: 10 years (typical) Notes: 1. program mode, the DATA should be latched in the CLK falling edge. 2. read mode, the DATA should be latched in before CLK low. 3. when in the read mode, must let P0IO.0 and P0.0 (DATA) set 1 ( input mode). 4. set GF1(general flag) to "1" will enable 1K flash. DC CHARACTERISTICS (VDD = 3V, VSS = 0V, TA = 25 C) PARAMETER Operating Voltage Flash ROM Operating Voltage Normal Mode Current Idle Mode Current Stop Mode Current Flash ROM Operating Current Input Voltage Output Current High-drive Port Output Current P1.5 ~ P1.7 High Low Sink Drive Sink Drive SYM. VDD VFLASH INORMAL IIDLE ISTOP IOP VIH VIL IOL IOH IOL IOH CONDITIONS MIN. LIMITS TYP. UNIT MAX. No load, decoder and CPU operating at 76.8K Hz No load, main clock, decoder on, CPU off No load, OSC stop In read mode DATA open All input pins VOL = 0.3V VOH = 2.7V VOL = 0.3V VOH = 2.7V 2.4 2.5 100 25 3.6 3.6 V V A 60 1 A A mA V V mA mA mA mA 2.0 -0.3 5 VDD 0.8 0.6/0.1 -1 4 -4 - - 31 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 FLASH ROM AC CHARACTERISTICS (VDD = 3V, VSS = 0V, TA = 25 C) PARAMETER MODE Pulse Width CTRL Pulse Width Clock Frequency of ADDR Clock Frequency of CLK Clock Ffrequency of CTRL Interval Between ADDR End & CLK Begin Interval Between CLK & CTRL Interval Between ADDR & CTRL Interval Between Addressing End & Block-erase Begin Interval Between MODE Rising Edge & CTRL Clock Begin Interval Between CTRL Clock End & MODE Falling Edge Interval Between MODE Falling Edge & Another Pin Active Data Access Time Data Set-up Time Data Hold Time SYMBOL TMP TWP FADDR FCLK FCTRL TI TGCC TGCA TAE TMB CONDITIONS Page coding mode Read/Write mode Write mode Page coding mode Block erase mode Mode selection MIN. 1 400 1 1 1 1 500 TYP. - MAX. 700 1 1 1 - UNIT S S MHz MHz MHz S S S S nS TME Mode selection 500 - - nS TGM - 1 - - S TRA TWS TAS TRH TWH TAH Read mode Write mode Read mode Write mode Write mode Whole-chip-erase mode Block-erase mode 250 250 0 10 10 400 45 40 - 500 50 45 nS nS nS nS nS nS S mS mS Programming Duration Whole-chip-erase Time Block-erase Time TPR TWE TBE - 32 - Preliminary W928C73 APPLICATION CIRCUIT Key2 VDD Key1 76.8K 10 PF Key0 VDD X I N 2 X O U T 2 VI DN DT 3 2 I N T 3 1 I N T 3 0 C O M 3 C O M 2 C O M 1 CPPPV O 2.7 2.6 2.5 3 M P 0 2.4 P 2.3 / S E G 35 P 2.2 / S E G 34 Vss RESET SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 Motor Buzzer LED From RF bat_det Signal_in RFEN QC PLEN VDD P1.5 P1.6 P1.7 BL_RF DI BS1 BS2 BS3 EA TEST1 (NC) TEST2 (NC) PSEN (NC) W928C73 64 LQFP SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 PLL/EP_1 PLL/EP_2 PLL/EP_3 P3.0 P3.1 P 3.2 / I N T 0 SEG14 P 3.3 / V 1.5 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9 S E G 10 S E G 11 S E G 12 S E G 13 Battery detector - 33 - Publication Release Date: June 2000 Revision A1 Preliminary W928C73 Headquarters Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change withou t notice. - 34 - |
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